This disclosure relates generally to a mat compress circuit, and more particularly to a mat compress circuit conducting a mat compression test in a semiconductor memory device.
Generally, after completing the fabrication of semiconductor memory devices, a test operation is conducted to find any malfunctions or defective states in the devices by writing data of high or low levels (e.g., ‘1 ’and ‘0 ’) into all memory cells and reading out the data from the memory cells in sequence. As the number of memory cells is continues to increase along with higher integration density of semiconductor memory devices, the test time for finding malfunctions in the memory cells increases, which is problematic.
To solve such a problem in testing the memory cells, a mat compression test scheme capable of finding malfunctions from a plurality of memory cells at the same time has been proposed. The above mat compression test is different from the former scheme that respectively screens memory cells in sequence.
The mat compression test is conducted, for the purpose of reducing a test time, by grouping mats of each bank into up and down banks and concurrently executing writing and reading operations to a plurality of memory cells after activating word lines included in the up and down banks. The mat compression test operation described above is shown in FIG. 1.
Referring to FIG. 1, a semiconductor memory device having four banks in the integration density of 128 Mb is comprised of first through eleventh mats MAT<1:11>. Each mat has first through third blocks. Each mat is formed of 128 (=27) word lines. In the first through eleventh mats MAT<1:11>, each of the blocks from the first block of the first mat MAT<1> to the first block of the sixth mat MAT<6> are grouped into the up bank, while the each of the blocks from the second block of the sixth mat MAT<6> to the last block of the eleventh mat MAT<11> are grouped into the down bank.
In applying the mat compression test to the semiconductor memory device of the up and down banks shown in FIG. 1, the word lines belonging to the up and down banks are selected one by one in compliance with an up/down bank selection address A<11> and first through fourth block addresses A<7:10>. With two activated word lines, data are concurrently written into corresponding memory cells of the up and down banks. And then, input/output switching signals operate to read out the data from the down bank after reading the data from the up bank. Through this, it is possible to concurrently determine the states of two memory cells coupled to the activate word lines.
However, for the sixth mat MAT<6> in which the first block is included in the up bank while the second and third blocks are included in the down bank, there could be a malfunction during the mat compression test. This will be described in greater detail below.
If the first through fourth block addresses A<7:10> are all set on high levels, the first block of the sixth mat MAT<6> is selected. To conduct the reading and writing operations to the first block of the sixth mat MAT<6>, it is required to turn all of the sixth and seventh input/output switches (not shown) for controlling data input/output of the sixth mat MAT<6>.
Here, a control signal turning on the sixth input/output switch is arranged to be active, or high, when a mat of the up bank is selected, while a control signal turning on the seventh input/output switch is arranged to be active when a mat of the down bank is selected. Thus, the seventh input/output switch may not be turned on when the first block of the up bank is selected, although it must be enabled to select the first block of the sixth mat MAT<6>. Such a problem is usually occurs in a semiconductor memory device integrated in density of 256 Mb, rather than other devices of 512 Mb or 1 Gb in which memory cells are grouped into 44 or 88 mats by a multiple of 4.